1. Field of the Invention
The present invention relates generally to a design tool of a semiconductor integrated chip. More particularly, the present invention relates to a method of extracting the interconnection capacitance of a semiconductor integrated chip having a multi-layered interconnection and a recording medium for recording the same.
2. Description of the Related Art
Referring to FIGS. 1 and 2, a conventional process for forming a semiconductor integrated circuit having predetermined specifications/functions can be seen. First, a high level description language is used to specify the functional and logic designs of the integrated circuit, as is depicted in step 11. Next, as shown in step 12, a synthesis step occurs where the logic circuit is synthesized to a logic gate level circuit using an automatic synthesis tool. A preliminary timing analysis of the logic gate level circuit is performed as shown in step 13. Upon completing various verification steps to ascertain the accuracy of the logic gate level circuit and after satisfying all timing constraints at the gross level, a physical design step is carried out as depicted in step 14.
The physical design step 14 is illustrated in further detail by the flowchart depicted in FIG. 2. As can be seen, the physical design step 14 occurs in several steps. First, the logic gate level circuit described in step 12 of FIG. 1 is laid out in a layout design system (not shown) and unit elements are disposed in an optimum position which is determined in consideration of both the position of the unit elements and the operational relationship between them (step 21). At step 22, an extraction step occurs in which the RC of the interconnection lines for connecting the unit elements is extracted to form an interconnection delay model. However, it should be noted that in a multi-layered interconnection structure with a high density of semiconductor integrated circuits, parasitic capacitance is generated, which has a considerable effect on the operation of semiconductor integrated circuits. As a result, the present parasitic capacitance must be considered in the interconnection RC extraction in step 22.
Next, the interconnection delay model of step 22 is used, as is illustrated in step 23, to calculate signal delay. At step 24, a detailed timing analysis is performed. If the result of the timing analysis/simulation of step 24 verifies that the physical design is within the predetermined spec range, the final verification step for examining the application of the design rule is performed as illustrated in step 26, or alternatively, step 15 of FIG. 1. However, if the result verifies that the physical design is not within the predetermined spec range, the logic circuit must be re-designed (e.g., return to step 12) so that a circuit implementation meeting desired timing requirements can be synthesized. Steps 21 through 24 are then repeated.
Chemical mechanical polishing (CMP) as a planarization technique has been used to obtain multi-layered interconnection structures with high density semiconductor integrated circuits and device patterns. However, the thickness of an insulating layer that has been chemically and mechanically polished is affected by the density of patterns disposed under the insulating layer. In particular, during CMP, an interlevel insulating layer which covers a portion of the semiconductor having a low pattern density is more easily removed than an interlevel insulating layer that covers a portion of the semiconductor having a high pattern density. As a result, dishing occurs, which affects the planarization of the interlevel insulating layers and causes non-uniformity in the electric characteristics of semiconductor devices.
To solve the previously-described problems, dummy patterns, which are not included in the design of the semiconductor integrated circuits, are used in the manufacture of semiconductor integrated circuits. These dummy patters are filled into regions of the semiconductor circuit in which patterns are not formed. As illustrated in FIG. 3, a plurality of dummy patterns 35 are obliquely disposed between signal lines 31a and 31b. The dummy patterns 35 and the signal lines 31a and 31b may be placed either in an on-plane mode or in an off-plane mode. In addition, because the dummy patterns 35 are made of a metal, they can be grounded or they can float. Because it is difficult to ground the dummy patterns 35, in most designs of ASIC (Application Specification Integrated Circuit), the dummy patterns 35 remain floating.
As illustrated in FIG. 3, data for specifying the dummy patterns 35 includes widths wx and wy of the dummy patterns 35, distances sx and sy between adjacent dummy patterns 35, shifted distances tx and ty between the dummy patterns 35, a definable minimum distance bs between the dummy patterns 35 and the signal line to buffer the signal line and dummy pattern 35, and a minimum width wm of definable dummy extraction.
If dummy patterns 35 are formed between interconnection lines (i.e., signal lines) in an on-plane mode in a semiconductor integrated circuit having a multi-layered interconnection structure, parasitic capacitance caused by the dummy patterns 35 has to be considered in the interconnection RC extraction step (i.e., step 22 of FIG. 2). Estimation and consideration of the parasitic capacitance due to the dummy patterns 35 must be accurate in order to accurately estimate the whole operation of the semiconductor integrated circuit.
To extract the parasitic capacitance caused by the dummy patterns 35, data on the dummy patterns is processed and input to an RC extractor. Based on the data for specifying the interconnection lines and the processed data for specifying the dummy patterns, the RC extractor outputs the parasitic capacitance with respect to an interconnection structure in which the dummy patterns are combined with the interconnection lines.
However, it is difficult to process data on the dummy patterns and obtain an interconnection structure in which actual dummy patterns are combined with the interconnection lines. In addition, because the dummy patterns are modified into various forms depending on the kinds of RC extractors, it is difficult to directly apply the previously-described parasitic capacitance extraction method to all RC extractors. Furthermore, calculating the parasitic capacitance caused by the dummy patterns results in a considerable increase in the time required for extracting parasitic capacitance of the interconnection structure.
It is therefore desirable to provide a method of extracting the interconnection capacitance of a semiconductor integrated chip having a multi-layered interconnection that can be used regardless of the RC extractor and which overcomes the disadvantages of the known prior art.
To solve the above-described problems, it is an object of the present invention to provide a method of extracting the interconnection capacitance of a semiconductor integrated circuit that can be used regardless of the type of RC extractor.
It is another object of the present invention to provide a recording medium for recording the method of extracting the interconnection capacitance of a semiconductor integrated circuit.
It is a further object of the present invention to provide a method of extracting the interconnection capacitance in which the time required for extracting the interconnection capacitance is not increased due to the presence of dummy patterns in the semiconductor integrated circuit.
It is yet another object of the present invention to provide a recording medium for the method of extracting the interconnection capacitance when dummy patterns are present.
Accordingly, in at least one exemplary embodiment of the instant invention, there is provided a method of extracting the interconnection capacitance of a semiconductor integrated circuit that can be used regardless of the RC extractor used. In this embodiment, an interconnection structure composed of a plurality of signal lines and dummy conductive patterns disposed between the signal lines is made into data. Interconnection structure primitives are then made by changing portions of the dummy patterns into high-k dielectric materials. Data is generated on these interconnection structure primitives based on the interconnection structure data. Capacitance of the interconnection structure is then extracted by inputting data on the interconnection structure primitives to an RC extractor and operating the data. Thereafter, subsequent design works, e.g., calculating the delay time of the operation of a circuit using the extracted RC, are performed.
In at least one embodiment of the invention, the interconnection structure primitives include buffer dielectric layers which are formed along the signal lines and which have low dielectric constants between the high-k dielectric materials and the signal lines. In addition, the data on the interconnection structure primitives includes dielectric constants, widths of the high-k dielectric layers, widths of the dielectric constants, and widths of the buffer dielectric layers. The dielectric constants of the high-k dielectric layers are determined using the results of a 3-dimensional simulation of an interconnection structure, which is performed in consideration of the dummy patterns. The dielectric constants of the buffer dielectric layers are equal to the dielectric constants of the insulating layers which insulate the signal lines in the interconnection structure.
In another exemplary embodiment of the present invention, there is provided a recording medium for recording a method of extracting the interconnection capacitance of a semiconductor integrated circuit. The recording medium includes a program module for making an interconnection structure into data. Composed of a plurality of signal lines and dummy conductive patterns disposed between the signal lines. The recording medium also includes a program module for generating data on the interconnection structure primitives, which are made by changing portions of the dummy patterns into high-k dielectric materials. Finally, the recording medium includes a program module for extracting the capacitance of the interconnection structure by inputting data on the interconnection structure primitives to an RC extractor and operating the data.